`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:29:22 04/05/2014
// Design Name:   vga_test_with_game_logic
// Module Name:   X:/EC551_project/logic/t_proj13.v
// Project Name:  logic
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: vga_test_with_game_logic
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module t_proj13;

	// Inputs
	reg sprite;
	reg clk;
	reg reset;
	reg up;
	reg down;
	reg enemy1_generation;
	reg enemy2_generation;
	reg bullet_generation;

	// Outputs
	wire [2:0] red;
	wire [2:0] green;
	wire [1:0] blue;
	wire HS;
	wire VS;

	// Instantiate the Unit Under Test (UUT)
	vga_test_with_game_logic uut (
		.sprite(sprite), 
		.clk(clk), 
		.reset(reset), 
		.red(red), 
		.green(green), 
		.blue(blue), 
		.HS(HS), 
		.VS(VS), 
		.up(up), 
		.down(down), 
		.enemy1_generation(enemy1_generation), 
		.enemy2_generation(enemy2_generation), 
		.bullet_generation(bullet_generation)
	);
module t_projtest;

	// Inputs
	reg stop;
	reg clk;
	reg reset;
	reg up;
	reg down;
	reg enemy1_generation;
	reg enemy2_generation;
	reg bullet_generation;

	// Outputs
	wire [2:0] red;
	wire [2:0] green;
	wire [1:0] blue;
	wire HS;
	wire VS;

	// Instantiate the Unit Under Test (UUT)
	vga_test_with_game_logic uut (
		.stop(stop), 
		.clk(clk), 
		.reset(reset), 
		.red(red), 
		.green(green), 
		.blue(blue), 
		.HS(HS), 
		.VS(VS), 
		.up(up), 
		.down(down), 
		.enemy1_generation(enemy1_generation), 
		.enemy2_generation(enemy2_generation), 
		.bullet_generation(bullet_generation)
	);

	initial begin
		// Initialize Inputs
		sprite = 0;
		clk = 0;
		reset = 0;
		up = 0;
		down = 0;
		enemy1_generation = 0;
		enemy2_generation = 0;
		bullet_generation = 0;

	#5 clk=1; reset=1; 
	#5 reset=0;
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      always #5 clk=~clk;
endmodule
